Fast Fourier transform address generator

ABSTRACT

A for Fast Fourier Transform (FFT) address generator utilizes a butterfly counter to count a butterfly count for each butterfly stage of FFT in numerical sequence; and a stage counter to count a stage count for the butterfly stage of FFT in bit-shifting manner. A data address logic is coupled to the butterfly counter and the stage counter to receive the butterfly count and the stage count, and to generate a data address according to a first regularized logic function. A twiddle factor address logic is coupled to the butterfly counter and the stage counter to receive the butterfly count and the stage count, and to generate a twiddle factor address according to a second regularized logic function.

BACKGROUND OF THE INVENTION

The present invention relates to an FFT (Fast Fourier Transform) addressgenerator, and more particularly to an FFT address generator which hassimpler structure and higher speed than conventional models.

The FFT is probably one of the most important algorithms in digitalsignal processing (DSP) applications. There are two approaches forcomputing the transform: software implemented on a programmable DSP, anddedicated FFT processor development. Real-time DSP favors the use of thelatter, which offers parallel processing capability.

An FFT processor hardware system mainly consists of two parts: thebutterfly processor for arithmetic operation, and an address generatorfor the generation of read/write addresses. The address generatorprovides addresses of the operation data as well as the so-called"twiddle factors" W_(N) ^(k) for each butterfly calculation. As isknown, the FFT butterfly computation operates on data in sets of rpoints, where r is called the radix. A P-point FFT uses P/r butterflyunits per stage for log_(r) P stages. The computational result of onebutterfly stage is the input data of next butterfly stage.

To meet the requirements of different signal flow graphs and differentpoint numbers, the logic design of an FFT address generator iscomplicated, and arithmetic-logic-unit-like structures are often used.Addresses are generated through the execution of instructions. Thepropagation delay time of conventional FFT address generators isrelatively high.

SUMMARY OF THE INVENTION

Through the study of FFT signal flow graphs, it has been found by thepresent inventors that in FFT calculation, the rules of binary addressgeneration for the data and twiddle factors W_(N) ^(k) could beexpressed in Boolean expressions to simplify the electrical circuitdesign of the FFT address generator. Therefore, the primary object ofthe present invention is to provide an FFT address generator which hasthe advantages of smaller number of transistors and higher speed.

In accordance with the present invention, an address generator for a2^(m) -point FFT comprises:

a butterfly counting mechanism for counting a butterfly count (B_(m-2)B_(m-3) . . . B₀) for each butterfly stage of FFT in numerical sequence;

a stage counting mechanism for counting a stage count (R_(m-1) R_(m-2) .. . R₀) for the butterfly stage of FFT in bit-shifting manner;

a data address logic mechanism, coupled to the butterfly countingmechanism and the stage counting mechanism, for receiving the butterflycount (B_(m-2) B_(m-3) . . . B₀) and the stage count (R_(m-1) R_(m-2) .. . R₀), and for generating a data address (A_(m-1) A_(m-2) . . . A₀)according to a first predetermined logic function: ##EQU1## wherein S isa select signal for the upper/lower data addresses in a butterfly ofFFT; and

a twiddle factor address logic mechanism, coupled to the butterflycounting mechanism and the stage counting mechanism for receiving thebutterfly count (B_(m-2) B_(m-3) . . . B₀) and the stage count (R_(m-1)R_(m-2). . . R₀), and for generating a twiddle factor address (C_(m-2)C_(m-3) . . . C₀) according to a second predetermined logic function:

    (C.sub.m-2 C.sub.m-3 . . . C.sub.0)=R.sub.0 (000 . . . 0)+R.sub.1 (B.sub.0 00 . . . 0)+R.sub.2 (B.sub.0 0 . . . 0) + . . . +R.sub.m-1 (B.sub.m-2 B.sub.m-3 B.sub.m-4 . . . B.sub.0)

According to one feature of the present invention, the data addresslogic mechanism includes a bit-reversing mechanism for reversing thebits of the stage count (R_(m-1) R_(m-2) . . . R₀) before performing thedata address generation logic according to the first predetermined logicfunction, in case of the decimation-in-frequency FFT; and the twiddlefactor address logic mechanism includes a bit-reversing mechanism forreversing the bits of the butterfly count (B_(m-2) B_(m-3) . . . B₀)before performing the twiddle factor address generation logic functionaccording to the second predetermined logic, in case of the DIF FFT.

According to another feature of the present invention, the FFT addressgenerator further comprises a butterfly full logic mechanism, coupled tothe butterfly counting mechanism, for receiving the butterfly count(B_(m-2) B_(m-3) . . . B₀), and for generating a full signal to flag thelast butterfly calculation in a certain butterfly stage of FFT. The FFTaddress generator also comprises a stage full logic mechanism, coupledto the stage counting mechanism, for receiving the stage count (R_(m1)R_(m2) . . . R₀), and for generating a last signal to flag the lastbutterfly stage of FFT.

According to further feature of the present invention, the data addresslogic mechanism utilizes a pass-transistor array structure to implementthe first predetermined logic function. The twiddle factor address logicmechanism also utilizes a pass-transistor array structure to implementthe second predetermined logic function.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by reference to thefollowing description and accompanying drawings, which form an integralpart of this application:

FIG. 1 shows a well-known decimation-in-time type of signal flow graphfor an 8-point radix-2 FFT processor;

FIG. 2 shows a well-known decimation-in-frequency type of signal flowgraph for an 8-point radix-2 FFT processor;

FIG. 3 is a schematic block diagram of an FFT address generatoraccording to one preferred embodiment of the present invention;

FIG. 4 is a schematic electronic circuit diagram of a data address logicable to be used in the FFT address generator of FIG. 3;

FIG. 5 is a schematic electronic circuit diagram of a twiddle factoraddress logic able to be used in the FFT address generator of FIG. 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

On the basis of FFT in-place calculation, the basic function of an FFTprocessor hardware system is the provision of two types of signal flowgraphs of radix-2: decimation-in-time (DIT) and decimation-in-frequency(DIF). The DIT and DIF types of signal flow graphs have differentstructures and should be discussed separately. For radix-2 decimation, a2^(m-1) point FFT has m stages of decimation, and each stage involves2^(m-1) butterfly calculation. FIG. 1 shows a well-known DIT-type signalflow graph for an 8-point radix-2 FFT, and FIG. 2 shows a well-knownDIF-type signal flow graph for the 8-point radix-2 FFT. As clearly seenin FIGS. 1 and 2, the 8-point FFT has three butterfly stages I, II, andIII, and each stage involves four butterfly calculations. In the samestage, the butterflies can be calculated in an arbitrary order, but inorder to synthesize the rules of address generation, it is assumed thatthe butterflies are calculated from top to bottom sequentially.

At first, the DIT-type signal flow graph for 8-point radix-2 FFT isconsidered, and then the general rules of address generation areconcluded. The data addresses (α₂ α₁ α₀) for butterfly calculation ineach stage of decimation are listed in Table 1.

                  TABLE 1                                                         ______________________________________                                        The data addresses (a.sub.2 a.sub.1 a.sub.0)                                  for butterfly calculation in FIG. 1                                                    1st stage 2nd stage   3rd stage                                               X    X'       X      X'     X    X'                                  ______________________________________                                        butterfly count                                                               (b.sub.1, b.sub.0)                                                            0 0        0 0 0  0 0 1    0 0 0                                                                              0 1 0  0 0 0                                                                              1 0 0                             0 1        0 1 0  0 1 1    0 0 1                                                                              0 1 1  0 0 1                                                                              1 0 1                             1 0        1 0 0  1 0 1    1 0 0                                                                              1 1 0  0 1 0                                                                              1 1 0                             1 1        1 1 0  1 1 1    1 0 1                                                                              1 1 1  0 1 1                                                                              1 1 1                             stage count                                                                   (r.sub.2 r.sub.1 r.sub.0)                                                                0 0 1       0 1 0       1 0 0                                      ______________________________________                                         (X, X': the upper/lower data in the butterfly)                           

In order to analyze the rule, the addresses are written in binary form.The X column in Table 1 lists the addresses of upper data in thebutterfly while the X' column lists the addresses of lower data. Thebutterfly calculation is counted in each stage of decimation innumerical sequence as in the left column (b ₁ b₀). For example, thebutterfly count (b₁ b₀) counts from (00), (01 ), (10) to (1 1 ) in eachstage. The stage of decimation is counted in bit-shifting manner as inthe bottom row (r₂ r₁ r₀). For example, the stage count (r₂ r₁ r₀)counts from (001), (010) to (100) for first stage to third stage. Asnoted, only one bit of the stage count (r₂ r₁ r₀) is "1", and the otherbits are "0" in all conditions.

By observing and analyzing Table 1, it is found that there areregularities in the bits of data address (α₂ α₁ α₀) with respect to thebutterfly count (b₁ b₀) and the stage count (r₂ r₁ r₀). For theaddresses of the upper data, the bit in the data address (α₂ α₁ α₀)corresponding to the "1" bit in the stage count (r₂ r₁ r₀) is always"0," and the other bits in the data address (α₂ α₁ α₀) are identical tothe butterfly count (b₁ b₀). For the addresses of the lower data, thebit in the data address (α₂ α₁ α₀) corresponding to the "1" bit in thestage count (r₂ r₁ r₀) is always "1," and the other bits in the dataaddress (α₂ α₁ α₀) are identical to the butterfly count (b₁ b₀). Thus,the Boolean expressions of the data address (α₂ α₁ α₀) can besynthesized as follows: ##EQU2## wherein s is a select signal for theupper/lower data addresses in a butterfly. The select signal s equals"0" for the address of the upper data in a butterfly, and equals "1" forthe address of the lower data.

The complex constant W_(N) ^(k), called a "twiddle factor," is stored inread only memory (ROM), addressed by the binary values of the k (or someauxiliary "zero" bits are added to its end). The DIT-type signal flowgraph shown in FIG. 1 is still used for consideration, and it is assumedthat there are only four complex constants: W_(N) ⁰, W_(N) ¹, W_(N) ²,W_(N) ³ stored within the W_(N) ^(k) ROM in the addresses (00) (01),(10) and (11) respectively. The addresses (c₁ c₀) of twiddle factorsW_(N) ^(k) for butterfly calculation in each stage of decimation arelisted in Table 2.

                  TABLE 2                                                         ______________________________________                                        The addresses (c.sub.1 c.sub.0) of W.sup.k.sub.N                              for butterfly calculation in FIG. 1                                           b.sub.1 b.sub.0 + `0 0`                                                                 1st stage    2nd stage                                                                              3rd stage                                     ______________________________________                                        0 0 0 0   0 0          0 0      0 0                                           0 1 0 0   0 0          1 0      0 1                                           1 0 0 0   0 0          0 0      1 0                                           1 1 0 0   0 0          1 0      1 1                                           r.sub.2 r.sub.1 r.sub.0                                                                 0 0 1        0 1 0    1 0 0                                         ______________________________________                                    

For convenience of analysis, two auxiliary "zero" bits (00) are added tothe end of the butterfly count value (b₁ b₀) to form the eventualbutterfly count (b₁ b₀ 0 0).

By studying the regularity of the W_(N) ^(k) address (c₁ c₀) in Table 2,it is found as follows:

For each stage of decimation, the W_(N) ^(k) address (c₁ c₀) is alwaysequal to two sequential bits in the butterfly count (b₁ b₀ 0 0). As thedecimation goes to the next stage, the equivalent two bits of the W_(N)^(k) address (c₁ c₀) in the butterfly count (b₁ b₀ 0 0) go forward by abit. For example, as r₀ =1, (c₁ c₀)=(0 0); as r₁ =1, (c₁ c₀)=(b₀ 0); andas r₂ =1, (c₁ c₀)=(b₁ b₀), as clearly seen in Table 2.

From this regularity, the Boolean expression of the W_(N) ^(k) address(c₁ c₀) can be written together as a simple formula:

    (c.sub.1 c.sub.0)=r.sub.0 (00)+r.sub.1 (b.sub.0 0)+r.sub.2 (b.sub.1 b.sub.0)(2)

After the above-described regularities of the data and W_(N) ^(k)addresses for the DIT-type FFT of 8 points are synthesized, theequations (1) and (2) can be directly expanded to general conditions.For a decimation-in-time FFT of 2^(m) points, the stage count requires mbits (R_(m-1) R_(m-2) . . . R₀), and counts in bit-shifting manner byusing, for example, a left-shift register. The butterfly count requiresm-1 bits (B_(m-2) B_(m-3) . . . B₀), and counts in numerical sequence byusing, for example, an up counter. The data addresses have m bits(A_(m-1) A_(m-2) . . . A₀), and the W_(N) ^(k) addresses have m-1 bits(C_(m-2) C_(m-3) . . . C₀).

The equation (1) is expanded as: ##EQU3## wherein S is a select signalfor the upper/lower data addresses in a butterfly. The select signal Sequals "0" for the address of the upper data in a butterfly, and equals"1" for the address of the lower data.

The equation (2) is expanded as:

    (C.sub.m-2 C.sub.m-3 . . . C.sub.0)=R.sub.0 (000 . . . 0)+R.sub.1 (B.sub.0 00 . . . 0)+R.sub.2 (B.sub.1 B.sub.0 0 . . .0) +. . . +R.sub.m-1 (B.sub.m-2 B.sub.m-3 B.sub.m-4 . . . B.sub.0)             (4)

Through comparison of two types of signal flow graphs, it is found thatDIF FFT can also utilize the above-described address generation logic ofDIT FFT with a little modification. For a DIF FFT of 2^(m) points:

a. Reverse the bits of the stage count R[m-1:0] while the butterflycount B[m-2:0] remains unchanged, and using the same address generationlogic, i.e. Eq. (3), the data address of DIF FFT can be attained simply.

b. Reverse the bits of the butterfly count B[m-2:0] while the stagecount R[m-1:0] remains unchanged, using the same address generationlogic, i.e. Eq. (4), the constant W_(N) ^(k) address of DIF FFT can alsobe attained simply.

Following to the address generation logic described above, an addressgenerator for an FFT processor is designed and shown in FIG. 3,according to one preferred embodiment of the present invention. Theaddress generator for the FFT processor includes a butterfly counter 10,a stage counter 20, a first full logic or butterfly full logic 30, asecond full logic or stage full logic 40, a data address logic 50, and atwiddle factor W_(N) ^(k) address logic 60. The butterfly counter 10 isactivated by a clock signal CK₁ to count the butterfly count (B_(m-2)B_(m-3) . . . B₀) for each butterfly stage in numerical sequence, andoutputs the butterfly count (B_(m-2) B_(m-2) . . . B₀) at its outputterminals. The butterfly counter 10 may be implemented by any suitablecounter. The first full logic 30 is coupled to the butterfly counter 10to receive the butterfly count (B_(m-2) B_(m-3) . . . B₀), and is usedto generate a full signal FULL and a clock signal CK₂ at its outputterminals. When all bits of the butterfly count are -1," the full signalFULL goes high to flag the last butterfly calculation in a certainbutterfly stage, and the clock signal CK₂ also goes high. The stagecounter 20 is coupled to the first full logic 30, and is activated bythe clock signal CK₂ to count the stage count (R_(m-1) R_(m-2) . . . R₀)in bit-shifting manner, and outputs the stage count (R_(m-1) R_(m-2) . .. R₀) at its output terminals. The stage counter 20 may be implementedby any suitable shift register. The second full logic 40 is coupled tothe stage counter 20 to receive the stage count (R_(m-1) R_(m-2) . . .R₀), and is used to generate a last signal LASTS at its output terminal.When the most significant bit of the stage count turns to "1 ", the lastsignal LASTS goes high to flag the last stage of decimation during thetransform.

The data address logic 50 is coupled to the butterfly counter 10 and thestage counter 20 to receive the butterfly count (B_(m-2) B_(m-3) . . .B₀) and the stage count (R_(m-1) R_(m-2) . . . R₀), and performs thedata address generation logic expressed by the above-described equation(3) to generate the data address (A_(m-1) A_(m-2) . . . A₀) at itsoutput terminals. The twiddle factor address logic 60 is coupled to thebutterfly counter 10 and the stage counter 20 to receive the butterflycount (B_(m-2) B_(m-3) . . . B₀) and the stage count (R_(m-1) R_(m-2) .. . R₀), and performs the W_(N) ^(k) address generation logic expressedby the above-described equation (4) to generate the twiddle factoraddress (C_(m-2) C_(m-3) . . . C₀) at its output terminals.

A reset signal RESET may be connected to the butterfly counter 10 andthe stage counter 20 in order to reset the butterfly count (B_(m-2)B_(m-3) . . . B₀) and the stage count (R_(m-1) R_(m-2) . . . R₀). An FFTpoint signal POINT indicating the transform length of FFT may beconnected to the first full logic 30 and the second full logic 40 tocontrol the limit values of both full logic 30 and 40.

In order to adapt both of the DIT and DIF FFT algorithms, the dataaddress logic 50 may include a bit-reversing mechanism for reversing thebits of the stage count (R_(m-1) R_(m-2) . . . R₀) before performing thedata address generation logic, i.e. Eq. (3), in case of the DIF FFT. Thetwiddle factor address logic 60 may also include a bit-reversingmechanism for reversing the bits of the butterfly count (B_(m-2) B_(m-3). . . B₀) before performing the twiddle factor address generation logic,i.e. Eq. (4), in the case of the DIF FFT.

In terms of circuit design, for the logic mechanisms of the data andtwiddle factor address generation, it is convenient to utilize a MOS(Metal-Oxide-Semiconductor) pass-transistor array. This structure issimilar to the barrel shifter. After a study of the address generationlogic of equations (1), (2), (3), and (4), it will be found that alllogic functions are a summation of two-variable-multiplication items. Inaddition, all multiplication items include a logic variable R_(i)(i=0˜m-1), and only one in the R_(i) (i=0˜m-1) will be high in allconditions. Therefore, use of a pass-transistor array is suitable forthe address generation logic of Eqs. (1), (2), (3), and (4). Forexample, FIG. 4 shows an electrical circuit consisting of an array ofnine NMOS (N-channel MOS) transistor which is able to implement the dataaddress logic 50 for Eq. (1). FIG. 5 shows an electrical circuitconsisting of an array of six NMOS transistors that is able to implementthe twiddle factor address logic 60 for Eq. (2). As clearly seen inFIGS. 4 and 5, the logic variables R_(i) (i-0˜2) are connected tocontrol the gate electrodes of the transistors, and the logic variablesB_(j) (j=0˜1) and S are connected to the source/drain electrodes of thetransistors to achieve the logic functions of Eqs. (1) and (2). Itshould be understood by those skilled in the art that the electricalcircuits of FIGS. 4 and 5 can be simply expanded to achieve the logicfunctions of Eqs. (3) and (4) for FFT of 2^(m) points. Such apass-transistor array logic circuit greatly simplifies theimplementation of the address generation logic of the present inventionand decreases the number of transistors while reducing the propagationdelay time.

While the invention has been described in terms of what is presentlyconsidered to be the most practical and preferred embodiments, it is tobe understood that the invention need not be limited to the disclosedembodiments. On the contrary, it is intended to cover variousmodifications and similar arrangements included within the spirit andscope of the appended claims, the scope of which should be accorded thebroadest interpretation so as to encompass all such modifications andsimilar structures.

What is claimed is:
 1. An address generator for a 2^(m) -point FFTcomprising:a butterfly counting mechanism for counting a butterfly count(B_(m-2) B_(m-3) . . . B₀) for each butterfly stage of FFT in numericalsequence; a stage counting mechanism for counting a stage count (R_(m-1)R_(m-2) . . . R₀) for the butterfly stage of FFT in bit-shifting manner;a data address logic mechanism, coupled to said butterfly countingmechanism and said stage counting mechanism, for receiving saidbutterfly count (B_(m-2) B_(m-3) . . . B₀) and said stage count (R_(m-1)R_(m-2) . . . R₀), and for generating a data address (A_(m-1) A_(m-2) .. . A₀) according to a first predetermined logic function: ##EQU4##wherein S is a select signal for the upper/lower data addresses in abutterfly of FFT; and a twiddle factor address logic mechanism, coupledto said butterfly counting mechanism and said stage counting mechanismfor receiving said butterfly count (B_(m-2) B_(m-3) . . . B₀) and saidstage count (R_(m-1) R_(m-2) . . . R₀), and for generating a twiddlefactor address (C_(m-2) C_(m-3) . . . C₀) according to a secondpredetermined logic function:

    (C.sub.m-2 C.sub.m-3 . . . C.sub.0)=R.sub.0 (000 . . . 0)+R.sub.1 (B.sub.0 00 . . . 0)+R.sub.2 (B.sub.1 B.sub.0 0 . . . 0) +. . . +R.sub.m-1 (B.sub.m-2 B.sub.m-3 B.sub.m-4 . . . B.sub.0)


2. The FFT address generator as claimed in claim 1, wherein said dataaddress logic mechanism includes bit-reversing mechanism for reversingthe bits of said stage count (R_(m-1) R_(m-2) . . . R₀) beforeperforming the data address generation logic according to said firstpredetermined logic function, in case of the decimation-in-frequencyFFT; and wherein said twiddle factor address logic mechanism includesbit-reversing mechanism for reversing the bits of the butterfly count(B_(m-2) B_(m-3) . . . B₀) before performing the twiddle factor addressgeneration logic function according to said second predetermined logic,in case of the DIF FFT.
 3. The FFT address generator as claimed in claim2, further comprising a butterfly full logic mechanism, coupled to saidbutterfly counting mechanism, for receiving said butterfly count(B_(m-2) B_(m-3) . . . B_(O)), and for generating a full signal to flagthe last butterfly calculation in a certain butterfly stage of FFT. 4.The FFT address generator as claimed in claim 3, further comprising astage full logic mechanism, coupled to said stage counting mechanism,for receiving said stage count (R_(m-1) R_(m-2) . . . R₀), and forgenerating a last signal to flag the last butterfly stage of FFT.
 5. TheFFT address generator as claimed in claim 4, wherein said data addresslogic mechanism utilizes a pass-transistor array structure to implementsaid first predetermined logic function.
 6. The FFT address generator asclaimed in claim 4, wherein said twiddle factor address logic mechanismutilizes a pass-transistor array structure to implement said secondpredetermined logic function.